1) We have got the very first prototype of i.MX6 Rex module just Today 
2) We have successfully booted it up to Linux – Today
3) We have recorded the process of bringing the module up and we will share it with you soon …
4) Pictures are coming soon ….
Here is the first console output:
-Boot 2009.08 (Apr 25 2013 - 03:48:11)
CPU: Freescale i.MX6 family TO1.2 at 792 MHz
Thermal sensor with ratio = 181
Temperature: 35 C, calibration data 0x5774f169
mx6q pll1: 792MHz
mx6q pll2: 528MHz
mx6q pll3: 480MHz
mx6q pll8: 50MHz
ipg clock : 66000000Hz
ipg per clock : 66000000Hz
uart clock : 80000000Hz
cspi clock : 60000000Hz
ahb clock : 132000000Hz
axi clock : 264000000Hz
emi_slow clock: 132000000Hz
ddr clock : 528000000Hz
usdhc1 clock : 198000000Hz
usdhc2 clock : 198000000Hz
usdhc3 clock : 198000000Hz
usdhc4 clock : 198000000Hz
nfc clock : 24000000Hz
Board: i.MX6Q-SABRESD: unknown-board Board: 0x63012 [POR ]
Boot Device: NOR
I2C: ready
DRAM: 1 GB
MMC: FSL_USDHC: 0,FSL_USDHC: 1,FSL_USDHC: 2,FSL_USDHC: 3
Using default environment
In: serial
Out: serial
Err: serial
Net: got MAC address from IIM: 00:00:00:00:00:00
FEC0 [PRIME]
Hit any key to stop autoboot: 0
## Booting kernel from Legacy Image at 10800000 ...
Image Name: Linux-3.0.35-2508-g54750ff
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 3161728 Bytes = 3 MB
Load Address: 10008000
Entry Point: 10008000
Verifying Checksum ... OK
## Loading init Ramdisk from Legacy Image at 10c00000 ...
Image Name: uboot initramfs rootfs
Image Type: ARM Linux RAMDisk Image (gzip compressed)
Data Size: 4545835 Bytes = 4.3 MB
Load Address: 00000000
Entry Point: 00000000
Verifying Checksum ... OK
Loading Kernel Image ... OK
OK
Starting kernel ...
Uncompressing Linux... done, booting the kernel.
Linux version 3.0.35-2508-g54750ff (r65388@shlinux3) (gcc version 4.6.2 20110630 (prerelease) (Freescale MAD -- Linaro 2011.07 -- Built at 2011/08/10 09:20) ) #1 SMP PREEMPT Thu Apr 25 03:42:37 CST 2013
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c53c7d
CPU: VIPT nonaliasing data cache, VIPT aliasing instruction cache
.... and it continues ....