Video: iMX6 DDR3 memory layout – Preliminary connections

iMX6 Rex is moving ahead. Curious how the DDR3 preliminary layout has been done?

Watch this video. Apart from the memory layout process, it shows also component placement under CPU:

  • Michael

    Hi Robert,

    Thanks for sharing your work!

    Can you please elaborate on your DDR3 memory schematics and routing ?

    Is there any particular reason why DDR3 terminations has been left out of the schematics ?

    I noticed the DDR3 addr/ctrl routing is done with balanced T’s like in DDR2 routing, but
    DDR3 is a fly-by architecture normally externally terminated at the end
    of address/ctrl lines. Have you done any simulations showing waveforms ?

    I do not find Altium design rules specifying matched net lengths for bytes and
    addr/ctrl lines. Are you keeping track of those elsewhere than Altium ?

    Regards Michael

    • http://www.fedevel.com Robert Feranec

      Hi Michael,

      the PCB has not been finished yet. The currrent PCB version doesnt have length matching done yet.

      Freescale DDR3 design allows to chose between T-branch (termination resistors not required) or fly-by. For the length matching we will use an excel sheet (will be shared on this website).

      If you are interested, have a look at Freescale design guide: IMX6DQ6SDLHDG_hardware_development_guide.pdf (can be downloaded for example here: http://cache.freescale.com/files/32bit/doc/user_guide/IMX6DQ6SDLHDG.pdf )

      Have a nice day,
      - Robert